A Processor-In-Memory Architecture for Multimedia Compression

A Processor-In-Memory Architecture for Multimedia Compression

In this proposed project, we are developing a low complexity processor in memory (PIM) architecture for compressing the size of image and video. We can reduce the latency of SRAM and improve its bandwidth by integrating a Novel processing element with Static random-access memory (SRAM). To decrease the power, area, cost and complexity we proposed various PIM design techniques in this paper. A design methodology is provided by an analysis of the processing element capabilities and performance. The proposed architecture consumes very less area and gives higher output.


A Processor-In-Memory Architecture for Multimedia Compression


By using a multiplier-based application specific processor (ASP) the proposed architecture delivers higher output at very low cost and also reduces the complexity and power consumption.   This ASP is developed to calculate the key algorithms and operations, which are essential to process the image and video. In this paper we mainly focus on data path design.


We developed this project using VHSIC Hardware Description Language (VHDL).

VHSIC – Very High Speed Integrated Circuit


ModelSim XE III 6.4b: is required for Simulation.

Xilinx ISE 10.1: is required for Synthesis.

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