The Advanced High-performance Bus (AHB) is a member of AMBA (Advanced Micro controller Bus Architecture) family. This high performance bus is useful in the high clock frequency system modules. AHB supports connection between low-power peripheral macro cell functions and on-chip memories & off-chip external memory, the efficient connection of processors. The AHB performs as the high-performance system backbone bus. With the help of synthesis and automated test techniques, AHB is specified to ensure ease of use in an efficient design flow.
AHB ensures highly reusable peripheral and system macro cells can be travelled across a diverse range of IC processes and be suitable for the customized, standard cell and gate array technologies. Generally, an AMBA-based microcontroller contains a high-performance system backbone bus (AMBA AHB), which is able to support the external memory bandwidth, on which on-chip memory, the CPU and other Direct Memory Access (DMA) devices reside. AHB is a technology-independent high performance bus.
In this work, we developed the design of the Advanced High-Performance Bus protocol. Arbiter, Master, Slave and Decoder are the basic blocks of this AHB protocol. To confirm that at a time, only one master has access to the bus we used the arbitration mechanism. The address of each transfer is decoded by the AHB decoder. Then it sends a select signal for the slave that is involved in the transfer. We can adopt this AMBA-AHB protocol in all the application.
AMBA- Advanced High Performance Bus IP Block
We developed this project using VHSIC Hardware Description Language (VHDL).
VHSIC – Very High Speed Integrated Circuit
ModelSim XE III 6.4b: is used for Simulation.
Xilinx ISE 10.1: is used for Synthesis.
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