The picoProcessor (pP) is an 8-bit processor and it has separate instruction and data memories.
Instruction memory: The size of the instruction memory is 4K.
Data memory: The size of the data memory is 256 bytes.
The I/O devices can be addressed by picoProcessor using 256 input ports and 256 output ports. This processor contains eight 8-bit general purpose registers, they are r0 to r7. r0 ignores writes and it is always read as zero This processor also contain an interrupt return register, Zero(Z) & Carry(C) condition codes and a return address stack of depth 4. Based on the value in the program counter, instruction register will fetch the next instruction from the instruction memory. This process is called ‘fetch’ cycle.
A program counter updating logic block will increment the value of program counter. Decoding logic is used to decode the instruction fetched by the instruction register and later it will generate the required control signals and get registered. This series of process is called as Decode Cycle. The picoProcessor (pP) is an 8-bit processor. The corresponding execution units will be getting enabled based on the generated control signals. In the clock cycle the outputs will be get registered. This is the ‘execute’ cycle. Later these registered outputs are written to the memory in the ‘write back’ cycle or to the register file.
Pipeline architecture is employed. The instruction register fetches the next instruction from the instruction memory depending on the value in the program counter. This is the ‘fetch’ cycle .The program counter is incremented using a program counter updating logic block. The instruction fetched by the instruction register is decoded by a decoding logic and the required control signals are generated and are registered. This is the ‘decode’ cycle. Depending on the control signals generated, the corresponding execution units are enabled. The outputs are registered in the following clock cycle. This is the ‘execute’ cycle. The registered outputs are then written to the register file or the memory in the ‘write back’ cycle.
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
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