Adiabatic technique is used to minimize the energy dissipation in conventional CMOS circuits. Also this technique will recycle the energy stored at load capacitance instead of losing that energy as heat and minimizes the dissipation in PMOS network.
But variation in parameter will play an important role in this adiabatic technique. This parameter variation will analyze the energy consumption by using TSPICE simulations.
We will compare conventional CMOS logic for inverter and 2:1 multiplexer circuits with two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) during analysis of the energy consumption. The adiabatic technique is very useful for the low power application in specified frequency range.
Title: Adiabatic Technique for Energy Efficient Logic Circuits Design
ModelSim XE III 6.4b for Simulation.
Xilinx ISE 10.1 for Synthesis.
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